Methods for accelerated design to FPGA technology
PhD: Rasmus Abildgren
Casestory
1. Purpose of the project The purpose of this project is to reduce the development time for implementation of an algorithm in a heterogeneous processing environment by:
- using only one input description language in the entire implementation phase,
- being able, in an early state of the design process, to estimate the performance of an FPGA implementation of an algorithm,
- and make a proper partitioning between hardware (FPGA) and software (general purpose CPU) of an algorithm.
2. Background The demand of processing power increases faster than the speed of processors, whether in small portable devices, big data analysis systems or something in between. To overcome this problem, the industry has increased the use of modern FPGAs in their products. This has helped close the gap in processing power, but has not been without cost; the development time has increased due to the more complex structure of the system.
One of the reasons for the rise in development time is that the typical design and implementation of an algorithm on a FPGA is different from the design and implementation on a programmable CPU, and since not all parts of the algorithms have the potential for an FPGA implementation, it is necessary to analyse the algorithm for potential and make the partitioning.
To reach the optimal partitioning, it is necessary to have an estimate of the performance, area and energy consumption on the FPGA platform of the different parts of the algorithm compared with an implementation on a programmable CPU platform. But no such automatic estimating tool exists on the marked, and the best estimates therefore need a manual implementation of the algorithm.
The design process could therefore be improved if we could:
- get a proper estimate,
- standardise greater parts of the design steps,
- and make a better partitioning.
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